Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FPGAs, and also can compile to fast x86 test code using Terra.
Coverage decreased (-38.6%) to 34.855% when pulling 6d044e6684f563dda6465762550b9a7ad76697a2 on sparsewrite into 1ebcbbc0b7ae3342698b27ddce28e7eedf1b8939 on master.
Coverage decreased (-38.6%) to 34.855% when pulling 6d044e6684f563dda6465762550b9a7ad76697a2 on sparsewrite into 1ebcbbc0b7ae3342698b27ddce28e7eedf1b8939 on master.