Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FPGAs, and also can compile to fast x86 test code using Terra.
Coverage decreased (-38.0%) to 34.795% when pulling c349a2cda7540f5bcc61957614c57dc6a7473128 on regout into 6e40b669e2e3b97f4d4c919f064a65c4b42ef362 on master.
Coverage decreased (-38.0%) to 34.795% when pulling c349a2cda7540f5bcc61957614c57dc6a7473128 on regout into 6e40b669e2e3b97f4d4c919f064a65c4b42ef362 on master.