Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FPGAs, and also can compile to fast x86 test code using Terra.
Coverage decreased (-20.7%) to 48.427% when pulling 981ab4ec9be027d40befae0c2ab50b82ded7f471 on minorfix1210 into f47a72ef232fd6ca63da74d1c1655b9ded8cbc72 on master.
Coverage decreased (-20.7%) to 48.427% when pulling 981ab4ec9be027d40befae0c2ab50b82ded7f471 on minorfix1210 into f47a72ef232fd6ca63da74d1c1655b9ded8cbc72 on master.