Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FPGAs, and also can compile to fast x86 test code using Terra.
Coverage decreased (-19.0%) to 48.378% when pulling 861d12620ef53d01dda2b4e581735a230cabd068 on arbiter into e3fec5be6d760e63d9c45cf396bc06da8691b3b3 on master.
Coverage decreased (-19.0%) to 48.378% when pulling 861d12620ef53d01dda2b4e581735a230cabd068 on arbiter into e3fec5be6d760e63d9c45cf396bc06da8691b3b3 on master.