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jameshegarty / rigel

Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FPGAs, and also can compile to fast x86 test code using Terra.
MIT License
56 stars 9 forks source link

Added modules #135

Closed jameshegarty closed 5 years ago

jameshegarty commented 5 years ago

Added modules, and remade fifo/regs to be a module instead of 'registered'.

Hit some kind of weird tail call optimization bug in luajit 2.0.2 in rigel.newFunction?

coveralls commented 5 years ago

Coverage Status

Coverage decreased (-21.3%) to 48.145% when pulling 3886867acd866fb1b4d18be431b0477e5fe03f9e on modules2 into 2a8d95300a4984e9c7fb79f77d6ec057f053f223 on master.