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jameshegarty / rigel

Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FPGAs, and also can compile to fast x86 test code using Terra.
MIT License
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Named port connection 'taps' does not exist for instance 'pipeline' of module 'harnessaxi' #147

Open sergei-romanenko opened 5 years ago

sergei-romanenko commented 5 years ago

An attempt to run the example

make out/conv_wide_handshake_taps.zynq10vivado.bit

produces the following error:

[Synth 8-448] named port connection 'taps' does not exist for instance 'pipeline' of module 'harnessaxi'

because the module harnessaxi is generated without the parameter taps. (The same is true of a number of other examples)

module harnessaxi(input wire CLK, input wire ready_downstream, output wire ready, input wire reset, input wire [64:0] process_input, output wire [64:0] process_output);
jameshegarty commented 5 years ago

I think this is just a regression b/c I don't test things on FPGA automatically (unfortunately), so the FPGA harness has gotten out of date. I will do that soon and fix this issue. Thanks!

jameshegarty commented 5 years ago

Let me know if this is blocking you in the short term.

sergei-romanenko commented 5 years ago

No problem (for me). I've just made you aware about this issue.