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jameshegarty / rigel

Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FPGAs, and also can compile to fast x86 test code using Terra.
MIT License
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automagically support non-AXI-burst aligned sizes in AXI target #25

Open jameshegarty opened 7 years ago

jameshegarty commented 7 years ago

implement a wrapper to bring to nearest AXI burst size. Need to add a pad & crop to bring any pixel size up to burst size. Need to add infrastructure to pad/crop the input image & output image.

jameshegarty commented 6 years ago

With commit #105 , this sort of works, but is broken. Cycle count doesn't work if data is not byte aligned.

Order is: OverUnder(CycleCount(ChangeRate(DUT))) we use changerate to size the FN in/out to bus width. round up to next burst alignment cycleCount waits for a burst aligned write. The reader will read burst aligned, and start to read a second frame into the DUT. If DUT doesn't produce data, it may stall. When cycleCount writes out at burst aligned address (but this is NOT what the scripts expect).

Better idea perhaps is: OverUnder(padToBurst(cycleCount(ChangeRate(DUT))))

We need: A test that gets a non-burst aligned size due to decimation. IE reads 16x16 image, writes 15x15 (and is invalid on the first cycle, not the last)