Rigel for handshake, Systolic for static

jameshegarty / rigel

Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FPGAs, and also can compile to fast x86 test code using Terra.

MIT License

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Rigel for handshake, Systolic for static #38

Open jameshegarty opened 7 years ago

jameshegarty commented 7 years ago

Consider refactoring the system so that all static pipeline wiring happens in systolic, and all handshake wiring happens in Rigel (built on top of systolic). Currently, static pipeline wiring is allowed in Rigel as well, which kind of duplicates functionality...

jameshegarty commented 7 years ago

Supporting both these use cases in the Rigel IR makes it easier to write/easier to write compiler passes on...