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jameshegarty / rigel

Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FPGAs, and also can compile to fast x86 test code using Terra.
MIT License
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Multi-DRAM-Port Harness refactor #62

Open jameshegarty opened 7 years ago

jameshegarty commented 7 years ago

The harness should be changed to present N 'axi-like' ports. Then, different memory access patterns (& multiple memory ports) can be implemented inside rigel (& will behave the same in hardware and the simulator).

The final pipeline the user provides should have type Handshake(nil)->Handshake(nil). One input valid bit triggers the pipeline to start reading addresses for a frame. One output valid bit indicates frame is done.

jameshegarty commented 7 years ago

The user will also have to provide a map to indicate what memory addresses files should be mapped to. This can be serialized to a file, which can then be used to set up memory on the zedboard.

jameshegarty commented 7 years ago

There should be a new type for memory busses. We want to support modules like caches inside rigel, which will need to have a memory address bus interface. It will basically have a HS output port for addresses, and a HS input port for data. Can these just be built out of named types? (ie they don't need to be builtins)