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jamieiles / uart

Verilog UART
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simultion error #1

Closed manu427 closed 7 years ago

manu427 commented 7 years ago

untitled sir how i can add makefiles of this code in modelsim software when i run the code without makefile&.gitignore i got error as when i compiled succesfully code compied.when i load testbench forsimulation i got error as loading failed

jamieiles commented 7 years ago

This has only been tested with Icarus Verilog