Partly implement descriptor caches for segment registers

tkchia commented 1 year ago

This patch changes the internal implementation of the emulated segment registers, so that each segment register comprises

a visible portion, containing the selector value (protected/ long mode) or paragraph value (real mode), which is directly accessible via mov, push, etc.
a hidden portion, containing the segment base address.

This makes the implementation closer to what is described in the Intel SDM Volume 3A, §3.4.3 (Segment Registers).

This patch allows the third stage bootloader of "Game of Life" (https://github.com/glitzflitz/gameoflife) to run.

The Blinkenlights register display formatting is also changed: if any segment register bases are non-zero, Blinkenlights displays the visible segment value and the segment base for each segment register, e.g.

FS  0000 (@00000000)  DS  1fe0 (@0001fe00)  CS  1fe0 (@0001fe00)
GS  0000 (@00000000)  ES  1fe0 (@0001fe00)  SS  1fe0 (@0001fe00)

tkchia commented 1 year ago

I realize that this PR is rather intrusive; let me know if it may need a redo. Thank you!

ghaerr commented 1 year ago

Hello @tkchia,

Wow! Very nice. Does this work then complete the implementation of the x86 "unreal" mode, where real mode execution of instructions with 32-bit addresses (i.e. 16-bit instructions with addr32 prefix) will use the previously set via protected-mode GDT hidden base address of the referenced segment register for the address calculation?

Thank you!

tkchia commented 1 year ago

@ghaerr : I would say that this patch is more about filling in the implementation of good old protected mode.

jart / blink

Partly implement descriptor caches for segment registers #49