Additional typing rules

javathunderman / zinnia

An experiment in hardware accelerated DSLs and parallel algorithms for signal processing applications.

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Closed javathunderman closed 4 months ago

javathunderman commented 5 months ago

Should write down operational semantics at some point
Currently:
- Add types to vectors
  - Bit width
  - Slots
Statically verify comparisons are well typed (no int comparisons with mismatched widths)
Represent as Calyx std_reg/comb_1d_mem as needed
Bools -> isomorphic to 1 bit ints

javathunderman commented 4 months ago

Items on here should be done, unless there's anything else @fifty-six ? otherwise will close

fifty-six commented 4 months ago

Yeah, lgtm.