PrettyTable.add_rows method support divider Argument

[jingfeihu]

Is your feature request related to a problem? Please describe.

It's not friendly to add section divider when I add multi rows to table.

1.Current Implement:

table = PrettyTable()
table.field_names = [...]
for row in rows1:
    table.add_row(row , divider=((rows1.index(row) == (len(rows1) - 1)))
for row in rows2:
    table.add_row(row , divider=((rows2.index(row) == (len(rows2) - 1)))
...
for row in rowsx:
    table.add_row(row , divider=((rowsx.index(row) == (len(rowsx) - 1)))
print(table)

2. I hope to implement like this:

   table = PrettyTable()
   table.field_names = [.......]
   table.add_rows(rows1, divider=True)
   table.add_rows(rows2, divider=True)
   ...
   table.add_rows(rowsx, divider=True)
   print(table)

Describe the solution you'd like

Solution1: Setting divider while add_rows.

    def add_rows(self, rows, section_divider=False) -> None:
        for row in rows:
            per_row_divider = ((rows.index(row) == (len(rows) - 1)) and (section_divider == True))
            self.add_row(row, divider=per_row_divider)

Describe alternatives you've considered

Solution2: Setting divider while add_row or add_rows is finished. Allow user to access self._divider by index.

table.dividers()[index] = True
table.dividers()[index] = False

Additional context

Add any other context or screenshots about the feature request here.

+-------------+-------------+-------------+-------------+
|   RX_INTF   |   RX_CHIP   |   TX_CHIP   |   TX_INTF   |
+-------------+-------------+-------------+-------------+
| COMP1_RX0_N | UMAC4_RX6_P | UMAC4_TX6_N | COMP1_TX0_N |
| COMP1_RX1_N | UMAC4_RX7_N | UMAC4_TX5_P | COMP1_TX1_N |
| COMP1_RX2_N | UMAC4_RX4_N | UMAC4_TX4_N | COMP1_TX2_N |
| COMP1_RX3_N | UMAC4_RX5_N | UMAC4_TX7_N | COMP1_TX3_N |
+-------------+-------------+-------------+-------------+
| COMP2_RX1_N | UMAC3_RX7_N | UMAC3_TX4_P | COMP2_TX1_N |
| COMP2_RX2_N | UMAC3_RX5_N | UMAC3_TX6_P | COMP2_TX2_N |
| COMP2_RX3_N | UMAC3_RX6_P | UMAC3_TX5_P | COMP2_TX3_N |
| COMP2_RX4_N | UMAC3_RX0_P | UMAC3_TX0_N | COMP2_TX4_N |
| COMP2_RX5_N | UMAC3_RX2_P | UMAC3_TX2_N | COMP2_TX5_N |
| COMP2_RX6_N | UMAC3_RX1_P | UMAC3_TX1_N | COMP2_TX6_N |
| COMP2_RX7_N | UMAC3_RX3_N | UMAC3_TX3_N | COMP2_TX7_N |
+-------------+-------------+-------------+-------------+
| COMP3_RX0_N | CMAC2_RX0_P | CMAC2_TX0_N | COMP3_TX0_N |
| COMP3_RX1_N | CMAC2_RX1_N | CMAC2_TX1_P | COMP3_TX1_N |
+-------------+-------------+-------------+-------------+