lengross
commented
1 year ago I was using similar code, and I was able to reproduce this problem
The “cause” is that the FIFO has data in it after the DMA ends. It appears that the ADC continues to fill the FIFO for a bit after the DMA completes. The next call to start a DMA uses that "old" data.
To show this, put a print like this at the end of the rp_adc_test.py script:
print(f"{adc.FCS.LEVEL=} {adc.FCS.OVER=}")The buffer level will not be zero, and sometimes the fact that a buffer overflow has occurred (FCS.OVER = 1) will be seen The next time the DMA is called, the DMA starts using the "old" data in the FIFO.
One would think that the loop:
while adc.FCS.LEVEL:
x = adc.FIFO_REGshould clear out the FIFO, but because the adc.FCS.DREQ_EN = 1 statement occurs before that loop. it seems that when this is executed the DMA starts using the data that is already in the FIFO, transferring it to the adc_buffer
If you want to clear the old data, just move the adc.FCS.DREQ_EN = 1 statement after the while loop. You can see the effect of moving that statement by putting a printing x and adc.FCS.LEVEL in the while loop.
This will solve the “bad data” problem, but depending on what you are doing, this may or may not be a a good solution.
In order to get continuous data (no gaps in time) you probably will need to set up a two buffers ping-pong in the DMA controller - I believe that can be done.
rickado22
Hello @jbentham
Congratulations for the project that is capable the high speed capture ADC using DMA! That is amazing!
I tested your example
rp_adc_test.pybut I noticed that has something like garbage in the first 8 numbers of the list - are numbers that has no sequence for next on the list.Please, could you tell me what is wrong or if I'm doing something wrong?
I did just two modifications in your code:
Below are two tests running test on rp2:
Thank you in advance!