[Question]

[8BitDreams]

Hello, Nice project, one question though: why don't you use Edge Plating instead of pins? https://www.google.de/search?q=edge+plating&client=ms-opera-mobile&channel=new&espv=1&prmd=isvn&sxsrf=ALeKk01rqD1lCSgbkhO5PCww2UsZ1p_TVQ:1627104187872&source=lnms&tbm=isch&sa=X&ved=2ahUKEwjBnoW5-_rxAhXG_qQKHbIJC_IQ_AUoAXoECAMQAQ&biw=393&bih=687&dpr=2.75

[jbilander]

Hi Viktor,

It's because edge plating is very expensive in comparison. I'm trying to make ReAgnus as cheap as posssible and pin headers are very cheap. Also with this technique you effectively make your own J-leads with spring action meaning the pins can flex a little to adapt to the socket pins and give a solid connection. If it turns out this won't work for some reason then I will consider edge plating or maybe using a homebrew PLCC-84-plug like in https://thezippsterzone.com/2019/03/27/gime-x/

Regards, Jörgen

[kipper2k]

Progress looks good, i do like the idea of the wraparound pin header. Is the chip going to be "the one" if so i will buy a couple and test this out (if i can find them lol.) Good job!

[jbilander]

Hi kipper2k, it's highly likely it will be any of the 10 MAX U169 FPGAs. Hopefully the cheapest 10M02 if everything fits in that one.

For development we have some 10M16 (more LEs and pin compatible) and will later try and optimise down as far as possible. We haven't actually verified the PCB working yet, because of the chip shortage, but now we have some 10M16 to play with so hopefully we can get a board built soon. A ReAgnus-devboard PCB has been ordered too but not yet received.

[vitecd]

Hello, How is it going? Did you test it yet?

[jbilander]

Hi,

yes, Niklas has got it working. At least with a 10M16 FPGA. I only did the hardware design, he has done the hard part with actually implementing the Agnus logic in Verilog, which is not an easy task. You will have to ask him for details.

[nonarkitten]

I found that even without edge plating, it makes good contact. These were made by JLCPCB and there's surprisingly good continuity between them. I'm worried at how consistent this might be, but it's a start.

[kipper2k]

I think with a little "creativity" we can make it happen

[niklasekstrom]

@nonarkitten That looks very interesting!

What FPGA is that board using? Are there voltage level translator chips on the back side?

Can you take another photo that zooms in on the connections between the PCB and the PLCC socket? It's hard to see in the above photo as the connections are slightly out of focus.

Let us know if we can assist in some way. I adapted Minimig's Agnus implementation to ReAgnus and that seemed to work well. I suppose frenchshark is working on a more faithful implementation, which sounds like a good idea.

[nonarkitten]

@nonarkitten That looks very interesting!

What FPGA is that board using? Are there voltage level translator chips on the back side?

No.

Long story short, officially, the low-voltage ispMACH is 5V tolerant, the MachXO PCI pins are 5V tolerant with series resistor and the MachXO2 isn't at all. However, the IBIS model seems to imply that they're all the same two types of sysIO pins with some having strong clamping diodes and some (e.g., the so-called LV or PCI) having weak clamping diodes (all the rest) which are about 1/2 the current capacity of the strong ones.

I suspect they're all basically the same and Lattice hasn't bothered recertifying them for 5V (it is dead after all, right? Only STM and Cypress seem to care). Fun fact, I drove the UART on my AM3358 at 5V for days (hooked to an Arduino) and it caused no problems. It's all about the current.

This would imply that they are all 5V tolerant as long as we're under the clamping current. But when places say 5V tolerance they have to mean a real, full on 5V CMOS. But we know the Amiga is not "true" 5V it's pseudo-NMOS (~10K or 100K equivalent pull-up) or real NMOS with 4.7K pull ups. It is 5V TTL which is why the CBT[D]s work so well.

These signals already have crappy amounts of current reaching the pins so I'm almost leaning to them not being needed AT ALL on the Amiga. We're going to try that. Worst that happens, I release the magic smoke and try with them.

Can you take another photo that zooms in on the connections between the PCB and the PLCC socket? It's hard to see in the above photo as the connections are slightly out of focus.

This is the limit of my iPhone. I'll charge up the EOS and see if it can do better.

Let us know if we can assist in some way. I adapted Minimig's Agnus implementation to ReAgnus and that seemed to work well. I suppose frenchshark is working on a more faithful implementation, which sounds like a good idea.

I've looked at both and they're both semi-close. Having the schematics has helped and yeah, he's been working on redoing Agnus since we got them. I haven't looked closely enough at MiniMig's Agnus, but if it's Paula and Denise are any indication, there are probably some gross inefficiencies in there. I know timing is a mess.

Paula used multipliers for the 8-bit data and 6-bit volume when in reality it's just a 3.58MHz PDM and 55kHz PWM, AND-ed. The 8-bit is the carry out of an 8-bit adder and the final left/right out is a 2-bit adder of those. Saves tones of LUTs.

Denise strangely had the pixel bus MUX on the RGB side and splits the HAM and CLUT into two different blocks. The pixel bus should be MUXED before then and you can save a ton of LUTs merging the HAM and CLUT blocks into one.

But god, I'd kill to get the Denise and Paula schematics from Jeri.

And don't get me started on it's broken Gary implementation scattered all over the place. Getting my Gary board to work 100% revealed how utterly broken that is.

Where FrenchShark's implementation is nice is the SDRAM controller and DMA cache. I wanted to squeeze in some 133MHz pSRAM to substitute for motherboard DRAM and the timing is PRETTY tight to remain synchronous, so I've been reading up on how it works with SDRAM.

[nonarkitten]

LOL. Might need to clean the lens; there's a little bloom here.

[niklasekstrom]

These signals already have crappy amounts of current reaching the pins so I'm almost leaning to them not being needed AT ALL on the Amiga. We're going to try that. Worst that happens, I release the magic smoke and try with them.

Testing that sounds like a good plan!

I haven't looked closely enough at MiniMig's Agnus, but if it's Paula and Denise are any indication, there are probably some gross inefficiencies in there. I know timing is a mess.

See, this is where we differ. 😄 I couldn't care less about the implementation being inefficient, as long as it fits in the FPGA and has the same (correct) externally observable behaviors.

LOL. Might need to clean the lens; there's a little bloom here.

These pictures are a lot clearer, thanks! That looks really good.

[nonarkitten]

These signals already have crappy amounts of current reaching the pins so I'm almost leaning to them not being needed AT ALL on the Amiga. We're going to try that. Worst that happens, I release the magic smoke and try with them.

Testing that sounds like a good plan!

I will put everything on the ARP git site.

I haven't looked closely enough at MiniMig's Agnus, but if it's Paula and Denise are any indication, there are probably some gross inefficiencies in there. I know timing is a mess.

See, this is where we differ. 😄 I couldn't care less about the implementation being inefficient, as long as it fits in the FPGA and has the same (correct) externally observable behaviors.

I know, I'm a bit of a perfectionist here, but there may be compatibility corner cases that come from fixing this. Good enough counts with emulators, but I'm trying to preserve the original chips and that means copying the logic as close as we can as well (with clear limitation on the differences between FPGA and ASIC in mind).

That and size. Large FPGA are insanely overpriced right now and there's no good reason Agnus needs more than about 1300 LUTs, maybe a lot fewer. It's narrowly too big (probably) for the 1200 LUT version of the MachXO2, but the 2000 LUT version is plenty.

Anyway, I just came to show that edge plating isn't THAT hard and seems to work, not co-opt someone else's project.

[kipper2k]

I have a chip coming so i will build the beta and hopefully no smoke :). There may be ways to make better connections if the initial version doesn't work ok, it does look good though

[jbilander]

Great work nonarkitten!

Hopefully that edge-plating isn't too expensive?.

If that FPGA doesn't work out for some reason then perhaps this Gowin, link below, could be a good replacement, 100 pin LQFP (79 IO) 4608 LEs (pitch 0.5 mm). Easy to solder and 3.3V (The -UV versions are with built-in LDO for the 1.2V-core so you don't have to think about that when designing, only one 3.3 volatge regulator required). IO-pins can be set to LVTTL 3.3 in the tool, but you will need level shifters towards the Amiga I think.

https://eu.mouser.com/ProductDetail/GOWIN-Semiconductor/GW1N-UV4LQ100C6-I5?qs=wnTfsH77Xs6vp00qFbqNlg%3D%3D

Expected in stock 30-sep-22 :)

I'm using a Gowin FPGA in another Amiga-hobby-project at the moment and it works great so far. The dev. tools are very snappy to work with compared to Xilinx ISE 14.7 for example.

These are the different Gowin FPGA packages/versions at the moment:

Regards

[jbilander]

These are the Gowin FPGAs I had in mind for ReAgnus.

Notice how it says 80 I/O. That is exacly the amount of IO-pins needed for Agnus, four pins in Agnus are Power-pins (VCC/GND), but that would require to use all JTAG-pins etc as IOs which is possible...

Unfortunately the pinout differs between the two, so no easy upgrade/downgrade path, but I guess you could try and synthesize and see if it'll fit in a -UV2 and if that is the case then go with that one in the design (if you can source them from e.g. Mouser?).

[jbilander]

For information, the latest design 837X Rev 1C is now updated with castellated holes (branch _castellatedholes) and should be able to take a Gowin GW1N-UV9UG169C6/I5 as a drop-in replacement for the Intel 10 Max. Gerbers exist under Releases as pre-release and is completely untested. Would be fun to try though.

Pin assignment here: https://github.com/jbilander/ReAgnus/tree/main/docs

JLC can do assembly of this Gowin FPGA via the Global Sourcing function.