Open jbush001 opened 6 years ago
Add a non-maskable interrupt vector. Interrupt handling is in hardware/core/control_register.sv. The interrupt_mask register controls which can generate interrupt. Pick one of the interrupts and hard code its mask bit to 1.
Add a non-maskable interrupt vector. Interrupt handling is in hardware/core/control_register.sv. The interrupt_mask register controls which can generate interrupt. Pick one of the interrupts and hard code its mask bit to 1.