Changes to provide compatibility with VCS simulator.

[schuler1]

TOP.sv: TOP module for VCS simulation. Note: I can supply generic VCS compile and simulate scripts if desired, let me know.

sim_ps2.sv: Added logic declaration to output ports sim_sdmmc.sv and sim_sdram.sv: Fixed always_ff incompatibility with initial block verilator_tb.sv: Enumerated IO sources -- for some unknown reason VCS needs it verilator_tb.sv: Fixed logic incompatibility with inout declaration verilator_tb.sv: Fixed SDRAM_DATA_WIDTH use before declaration verilator_tb.sv: Fixed multiple drivers on m[1] when SIMULATE_VGA is defined verilator_tb.sv: Added $fwrite function for dumping in VCS (uses %c for endian independence)

[schuler1]

Need to figure out what went wrong with Travis CI.

[schuler1]

Getting Travis CI to run again.

[jbush001]

Shoot, I see what went wrong with TravisCI. I configured the Docker repo using a travis CI variable, but those aren't propagated for pull requests. I'll fix that in mainline, but we can skip that in the interim.

[jbush001]

Thanks! Does VCS need the top module to be called TOP? It might be clearer to call it top_vcs to be more descriptive (I guess that would need to be another PR since I just merged this one :). It seems like scripts would be helpful. It might also be good to add a quick note to the hardware/ README file indicating VCS is supported and how to use it.

[schuler1]

On Aug 3, 2017, at 8:02 PM, Jeff Bush notifications@github.com wrote:

Thanks! Does VCS need the top module to be called TOP?

Not necessarily. But TOP is how it shows up in the vcd when using Verilator. So in case anybody has existing wave file templates, they can be easily reused if the hierarchy names are preserved. It might be clearer to call it top_vcs to be more descriptive (I guess that would need to be another PR since I just merged this one :). It seems like scripts would be helpful.

Ok. I'll submit generic scripts in the next few days. I also have a vcsrun in the Mandelbrot makefile that I'll contribute. It might also be good to add a quick note to the hardware/ README file indicating VCS is supported and how to use it.

Will do.

Regards

Sergio

— You are receiving this because you modified the open/close state. Reply to this email directly, view it on GitHub, or mute the thread.

[jbush001]

Not necessarily. But TOP is how it shows up in the vcd when using Verilator. So in case anybody has existing wave file templates, they can be easily reused if the hierarchy names are preserved.

Makes sense. That also could be used as a top level module for other simulators, so using a generic name is probably better.