JTAG test intermittently fails with short socket read (part II)

[jbush001]

Continuation of issue #121. The symptoms there are more likely to be this problem (since the problem described and fixed there would cause a test failure, but it would be a timeout exception rather than a short socket read).

In the case where the test fails, I see this:

jtag_inject                             Random seed is 1512366910
cores 1|threads per core 4|l1i$ 16k 4 ways|l1d$ 16k 4 ways|l2$ 128k 8 ways|itlb 64 entries|dtlb 64 entries
Sending JTAG command 0x3 data 0x1
thread 0 rolled back to 0, cause 1 address 00001008
- core/writeback_stage.sv:535: Verilog $finish
received JTAG response 0x0

Somehow the act of asserting the JTAG halt signal seems to be causing a crash. Cause 1 is an illegal instruction.

[jbush001]

Probably a dup of #124, which injects spurious instructions. In this case, it was invalid.

[jbush001]

Retested with fix for #124, seems to be gone.