jbush001 / NyuziProcessor

GPGPU microprocessor architecture
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SD card initialization fails on FPGA #140

Closed jbush001 closed 6 years ago

jbush001 commented 6 years ago

Times out initializing card in SPI mode. It seems to never read anything but 0xff from the data out (DO) pin after sending CMD0.

  1. Connected pins to GPIO block. I verified I could read the input pins (printed to the serial log) by shorting the solder pads to ground, and drive output pins by controlling with software and measuring with a multimeter.
  2. I tried putting the chip into 4 bit mode. I could see correct data on DAT1-3, but DAT0 was stuck at VCC. I wrote various patterns on the SD card on my laptop, then re-read on the board to confirm.
jbush001 commented 6 years ago
SD Pin SD Mode SPI Mode FPGA PIN
1 CD/DAT3 CS PIN_AC14
2 CMD DI PIN_AD14
3 VSS1 VSS1
4 VDD VDD
5 CLK SCLK PIN_AE13
6 VSS2 VSS2
7 DAT0 DO PIN_AE14
8 DAT1 PIN_AF13
9 DAT2 PIN_AB14

Schematic for DE2-115 board:

schematic screen shot 2018-02-26 at 4 13 04 am screen shot 2018-02-26 at 4 14 37 am

Pin information from DE2-115 data sheet:

pin_mapping

SPI/SD pin mapping:

https://en.wikipedia.org/wiki/Secure_Digital#Transfer_modes

FPGA pin configuration:

https://github.com/jbush001/NyuziProcessor/blob/48f71f80f91e50ba7d54f324b76a6903f78c5538/hardware/fpga/de2-115/de2_115.qsf#L186-L189

I/O configuration:

https://github.com/jbush001/NyuziProcessor/blob/48f71f80f91e50ba7d54f324b76a6903f78c5538/hardware/fpga/de2-115/de2_115_top.sv#L62-L65

Mapping to SPI controller:

https://github.com/jbush001/NyuziProcessor/blob/48f71f80f91e50ba7d54f324b76a6903f78c5538/hardware/fpga/de2-115/de2_115_top.sv#L196-L202

jbush001 commented 6 years ago

Simulation waveforms. The times at the top aren't accurate, is they assume a clock speed of 1 GHz rather than the 50 MHz that board runs at. Here is the initialization clock sequence (80 clocks with CS high).

screen shot 2018-02-25 at 6 59 04 pm

Here is CMD0:

screen shot 2018-02-25 at 6 57 58 pm
01000000 00000000 00000000 00000000 00000000 10010101
40       00       00       00       00       95

Closeup showing bit phase:

phase

output in falling edge, sample on rising edge (mode 0)

jbush001 commented 6 years ago

Verified 250 system clocks per spi clock: 200kHz SPI clock at 50Mhz system clock. I tried slowing this down by increasing the divider on the dev board to ensure there wasn't an issue with clock speed, but there was no effect.

jbush001 commented 6 years ago

While waiting for response. CS is still low, DI is high.

screen shot 2018-02-25 at 7 12 26 pm
jbush001 commented 6 years ago

Tried with 3 cards, all failed in the same way (no response to initial CMD0)

jbush001 commented 6 years ago

I hooked up a logic analyzer and it responded to the first command.

screen shot 2018-03-02 at 5 56 32 pm

Unplugged the logic analyzer and it started failing again... Seems like this might be a connector issue.

(I should be sending CMD8 instead of CMD1 after CMD0, but that is a separate issue)

jbush001 commented 6 years ago

I also had to turn the board upside down to attach the probes. In the normal position, gravity pulls the card down away from the pins. Upside down, it pushes them against them. I might try sticking a piece of paper in with the card to apply more pressure.

jbush001 commented 6 years ago

I tried sticking paper in, turning the board over with no success. However, it works consistently if the probes are attached...

screen shot 2018-03-03 at 11 38 01 am
travisg commented 6 years ago

Hmm, what board is that BTW?

jbush001 commented 6 years ago

DE2-115

travisg commented 6 years ago

Ah didn't know if you were still using that. I actually bought one of those for myself when this project got started up years ago. I should brush it off.