Assertion: multiple way hits in DTLB while booting xv6

[jbush001]

While booting xv6: https://github.com/jbush001/xv6-nyuzi

$ nyuzi_vsim +block=fs.img +bin=kernel.hex

[169113848] %Error: tlb.sv:234: Assertion failed in TOP.soc_tb.nyuzi.core_gen[0].core.dcache_tag_stage.dtlb %Error: /Users/jeffbush/src/NyuziProcessor/hardware/core/tlb.sv:234: Verilog $stop

[jbush001]

One way of reproducing this is to insert a non-global page into one ASID, then insert a global page with a different ASID at the same address. This may be happening because the initial page tables are set up in boot code with the global flag set, but later code does not use it. When two threads are running in different address spaces, they could reproduce this sequence.