The following conditions are currently not handled properly:
The instruction queue is full when the host attempts to inject an instruction
A multi-cycle instruction (scatter/gather load/store) is active when the OCD halts and it takes a rollback before finishing.
A halt between two issues of a non-interruptible function (synchronized memory operation or I/O memory transfer).
To address this, the status register should return a busy indication (probably change the identifier from ISSUED to BUSY), and this should be indicated if:
ts_fetch_en is false for the selected thread
ior_pending, dd_load_sync_pending, or sq_store_sync_pending is set (There is similar logic in instruction_decode_stage)
Also need additional logic in thread_select_stage to check if a multi-cycle instruction is pending.
The following conditions are currently not handled properly:
To address this, the status register should return a busy indication (probably change the identifier from ISSUED to BUSY), and this should be indicated if:
Also need additional logic in thread_select_stage to check if a multi-cycle instruction is pending.