To fully verify #62, it should be run on FPGA. Need the following.
Expose via one of the GPIO headers on the board
Find some (ideally open) hardware JTAG unit (or perhaps synthesize an integrated JTAG host in FPGA with a bridge that connects to some other external interface, but using a separate hardware JTAG is preferable to validate interoperability).
To fully verify #62, it should be run on FPGA. Need the following.
Optionally: