Coprocessor memory interface

[jbush001]

Currently, the only way to access external coprocessors is to use the I/O bus. Writes to addresses at high physical memory addresses, instead of going through the normal cache hierarchy, are redirected to the I/O bus. While this is useful for relatively low-speed peripherals, it has performance limitations when used with coprocessors such as texture fetch units:

• It can only write a single, 32-bit word at a time. For vectorized compute code, this requires 32 instructions to copy a vector value into our out of it (getlane/write).
• It takes a rollback for every read or write, since the I/O bus is shared by all cores and transactions need to globally arbitrate
• There is no way for peripherals to make a thread wait for them to be ready, so threads must poll them, which wastes processor cycles and clogs up the bus
• The bus does not have a concept of thread IDs, which requires some form of arbitration at the software or coprocessor level.

The proposal is to create a new bus for use in high-speed peripherals. This would not replace the low speed bus, but would address different use cases and constraints.

Design here: https://gist.github.com/jbush001/09f51178a366c0f6b8f07363c30f414f

[jbush001]

Prototype implementation here: https://gist.github.com/jbush001/636812836911d5c7873893a1d0ae517e

[jbush001]

A few alternatives (which are not mutually exclusive):

• Have a chunk of shared SRAM, accessible both by coprocessors and the nyuzi cores.
• Create a general purpose coprocessor instruction that has an operation field.

[jbush001]

On SRAM: this solution would look similar to the proposal in implementation, and could be implemented using the proposal. However, the proposal is more general. On instruction: one big issue is that an access control model would need to be defined. The instruction could be made supervisor-only, but that might incur an unreasonable performance penalty for some configurations. The advantage of memory mapping is that the existing MMU access control model can be reused.