Hardware MMU page table walker

jbush001 / NyuziProcessor

GPGPU microprocessor architecture

Apache License 2.0

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Hardware MMU page table walker #76

Open jbush001 opened 7 years ago

jbush001 commented 7 years ago

Currently, when a TLB miss occurs, it raises a trap and software walks the page table and fills in the TLB entry. This feature would perform that walk in hardware to reduce the overhead.

jbush001 commented 6 years ago

This would be a block within each core
It would communicate with the L2 cache via the l1_l2_interface to load page directories and tables from memories.
There would need to be another signal to block and wake threads when TLB misses are pending.