jbush001 / NyuziToolchain

Port of LLVM/Clang C compiler to Nyuzi parallel processor architecture
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Generate masked forms for sext8/sext16 #86

Open jbush001 opened 7 years ago

jbush001 commented 7 years ago

In lib/Target/Nyuzi/NyuziInstrInfo.td, SEXT8VS, SEXT8VVM, SEXT8VSM, SEXT16VS, SEXT16VVM, an SEXT16VSM have their instruction matching patterns commented out, e.g.:

  def SEXT16VSM : FormatRMaskedOneOpInst<
    (outs VR512:$dest),
    (ins GPR32:$mask, GPR32:$src2, VR512:$oldvalue),
    "sext_16_mask $dest, $mask, $src2",
    [/*(set v16i32:$dest, (vselect v16i1:$mask, (sext_inreg (splat i32:$src2), i16),
      VR512:$oldvalue))*/],
    0x1e,
    FmtR_VVSM,
    II_INT>;

If the patterns are left in, TableGen complains with a type inference error:

SEXT16VSM:  (set v16i32:<empty>:$dest, (vselect:{v16i1:v16i32:v16f32} v16i1:v16i1:$mask, (sext_inreg:{v16i1:v16i32} (splat:<empty> i32:<empty>:$src2), i16:Other), VR512:{v16i1:v16i32:v16f32}:$oldvalue))
Included from /Users/jeffbush/src/NyuziToolchain/lib/Target/Nyuzi/Nyuzi.td:23:
/Users/jeffbush/src/NyuziToolchain/lib/Target/Nyuzi/NyuziInstrInfo.td:136:3: error: In SEXT16VSM: Type inference contradiction found, '{v16i1:v16i32}' needs to be scalar
  def SEXT16VSM : FormatRMaskedOneOpInst<
  ^
Assertion failed: (isConcrete() && "Type isn't concrete yet"), function getConcrete, file /Users/jeffbush/src/NyuziToolchain/utils/TableGen/CodeGenDAGPatterns.h, line 74.

This doesn't break anything: when the patterns are commented out, LLVM just inserts an extra move instruction. Because this instruction occurs rarely, the performance impact is probably miniscule. But it would be good to understand why this is failing and fix it.