I was reading through the FPGA code to understand how the counters work when I noticed that, as currently implemented, the rectangular counter only gives a new reading every other gate cycle. I checked the output, and as seen in the plot below, all of the rectangular counts are paired together with a new value every 2 seconds. This means that the current 1 second gate time of the rectangular counter is paired with 1 second of dead time between counts.
The easiest fix would be to uncomment out lines 200 through 202 in "dual_type_frequency_counter.vhd". This would restore the correct interleaving behavior of the two counter instances.
Above this section of code there is a note,
using only counter 1 is sufficient ok since the integration runs for half as long (the triangle lasts 2N, while the rectangle lasts N)
but as implemented in lines 82 through 91 of "triangular_frequency_counter.vhd" the output value of the rectangular counter is only updated at N and not at 2N. And even though the counter value doesn't get updated at 2N, the "output_clk_enable_N_times_faster" variable is still flipped every gate cycle ("dual_type_frequency_counter.vhd" line 118), which causes the "zdtc_samples_number_counter" variable to increment indicating that a new value has become available ("dpll_wrapper.v" line 574 and 1437). The old value is then read in place of a new one producing the double valued behavior as seen in the plot.
In order for one counter to be sufficient you would have to change the behavior of "triangular_frequency_counter.vhd" when in rectangular mode to output the new counter value and restart the integration at every gate cycle.
I was reading through the FPGA code to understand how the counters work when I noticed that, as currently implemented, the rectangular counter only gives a new reading every other gate cycle. I checked the output, and as seen in the plot below, all of the rectangular counts are paired together with a new value every 2 seconds. This means that the current 1 second gate time of the rectangular counter is paired with 1 second of dead time between counts.
The easiest fix would be to uncomment out lines 200 through 202 in "dual_type_frequency_counter.vhd". This would restore the correct interleaving behavior of the two counter instances.
Above this section of code there is a note,
but as implemented in lines 82 through 91 of "triangular_frequency_counter.vhd" the output value of the rectangular counter is only updated at N and not at 2N. And even though the counter value doesn't get updated at 2N, the "output_clk_enable_N_times_faster" variable is still flipped every gate cycle ("dual_type_frequency_counter.vhd" line 118), which causes the "zdtc_samples_number_counter" variable to increment indicating that a new value has become available ("dpll_wrapper.v" line 574 and 1437). The old value is then read in place of a new one producing the double valued behavior as seen in the plot.
In order for one counter to be sufficient you would have to change the behavior of "triangular_frequency_counter.vhd" when in rectangular mode to output the new counter value and restart the integration at every gate cycle.