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jdryg / tis100cpu

TIS-100 CPU in VHDL
MIT License
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Feature proposal: Node performance counters #6

Open holmak opened 9 years ago

holmak commented 9 years ago

In the game, each node displays a utilization percentage that indicates how much time it spent executing instructions versus waiting for an input. This is useful for optimization, since it indicates where the bottlenecks are. Since you have to detect port-stalls anyway, it seems like it would be easy to also increment a counter when this happens. There would then have to be some kind of chip-wide network to retrieve and reset the performance counters.

This obviously isn't necessary, but it would be neat since it is in the game.

tis performance counter

jdryg commented 9 years ago

Agreed that would be nice :)

One question: Percentage of idle time is the number of cycles waiting for a port to the total number of cycles the node is running, correct?

In other words, what's needed is 2 counters. One to count the total cycles and one to count the number of cycles (srcA_isPort AND (NOT isReadPortReady)) OR (dst_isPort AND (NOT isWritePortReady)) is true, right?

holmak commented 9 years ago

I'm not sure exactly what the calculation is, but I think it is close to what you said; (idle / total).

You are right that it would require a "total cycles" counter, but that could be global rather than per-node, since all of the clocks advance synchronously.