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jeanthom / gram

DDR3 controller for nMigen (WIP)
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DQS group mismatch #11

Closed jeanthom closed 4 years ago

jeanthom commented 4 years ago 
ERROR: DQS group mismatch, port DQSW270 of 'ddrphy.U$$26' in group LDQ41 is driven by DQSBUFM 'ddrphy.U$$25' in group LDQ77
ERROR: Packing design failed.
0 warnings, 2 errors
Traceback (most recent call last):
  File "headless-ecpix5.py", line 240, in <module>
    platform.build(soc, do_program=True)
  File "/home/jeanthomas/.local/lib/python3.8/site-packages/nmigen/build/plat.py", line 94, in build
    products = plan.execute_local(build_dir)
  File "/home/jeanthomas/.local/lib/python3.8/site-packages/nmigen/build/run.py", line 95, in execute_local
    subprocess.check_call(["sh", "{}.sh".format(self.script)])
  File "/usr/lib64/python3.8/subprocess.py", line 364, in check_call
    raise CalledProcessError(retcode, cmd)
subprocess.CalledProcessError: Command '['sh', 'build_top.sh']' returned non-zero exit status 255.
jeanthom commented 4 years ago
jeanthom commented 4 years ago

Removing U$$26 from the rtlil sources causes the following error to appear:

Warning: Wire top.\pin_ddr3_0__dm.ddr3_0__dm__o [0] is used but has no driver.
ERROR: DQS group mismatch, port DQSW270 of 'ddrphy.U$$71' in group LDQ41 is driven by DQSBUFM 'ddrphy.U$$70' in group LDQ89
ERROR: Packing design failed.
0 warnings, 2 errors

Both U$$26 and U$$71 are ODDRX2DQA instances for DM signals.

jeanthom commented 4 years ago

U$$26 and U$$71 are instantiated here: https://github.com/jeanthom/gram/blob/master/gram/phy/ecp5ddrphy.py#L342-L352

jeanthom commented 4 years ago

DM pinout seems buggy.

jeanthom commented 4 years ago

Fixed in https://github.com/jeanthom/gram/commit/44a5668293ee2e4009d80f820ecd6506cd30195e