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jeanthom / gram

DDR3 controller for nMigen (WIP)
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Critical path too long in dram core #13

Closed jeanthom closed 4 years ago

jeanthom commented 4 years ago 
Info: Critical path report for clock '$glbnet$sysclk_clk' (posedge -> posedge):
Info: curr total
Info:  0.4  0.4  Source dramcore.controller.refresher.sequencer.count_LUT4_C_Z_L6MUX21_Z_SD_LUT4_Z_4_SLICE.Q1
Info:  0.7  1.1    Net dramcore.controller.refresher.zqcs_timer.count[16] budget 0.197000 ns (21,92) -> (21,92)
Info:                Sink dramcore.controller.refresher.sequencer.count_LUT4_C_Z_L6MUX21_Z_SD_LUT4_Z_4_SLICE.A0
Info:  0.2  1.3  Source dramcore.controller.refresher.sequencer.count_LUT4_C_Z_L6MUX21_Z_SD_LUT4_Z_4_SLICE.F0
Info:  1.0  2.3    Net dramcore.controller.refresher.sequencer.count_LUT4_C_Z_L6MUX21_Z_SD[2] budget 0.197000 ns (21,92) -> (18,89)
Info:                Sink dramcore.controller.refresher.sequencer.count_LUT4_C_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_SLICE.D1
Info:  0.3  2.6  Source dramcore.controller.refresher.sequencer.count_LUT4_C_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_SLICE.OFX0
Info:  0.0  2.6    Net dramcore.controller.refresher.sequencer.count_LUT4_C_Z_L6MUX21_Z_D1_L6MUX21_Z_D1 budget 0.000000 ns (18,89) -> (18,89)
Info:                Sink dramcore.controller.refresher.sequencer.count_LUT4_C_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_SLICE.FXB
Info:  0.2  2.8  Source dramcore.controller.refresher.sequencer.count_LUT4_C_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_SLICE.OFX1
Info:  0.0  2.8    Net dramcore.controller.refresher.sequencer.count_LUT4_C_Z_L6MUX21_Z_D1 budget 0.000000 ns (18,89) -> (18,89)
Info:                Sink dramcore.controller.refresher.sequencer.count_LUT4_C_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_SLICE.FXB
Info:  0.2  3.0  Source dramcore.controller.refresher.sequencer.count_LUT4_C_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_SLICE.OFX1
Info:  1.3  4.2    Net dramcore.controller.refresher.sequencer.count_LUT4_C_Z[0] budget 0.196000 ns (18,89) -> (13,79)
Info:                Sink dramcore.controller.U$$0.row_opened_LUT4_D_1_Z_L6MUX21_Z_D1_PFUMX_Z_SLICE.D0
Info:  0.3  4.5  Source dramcore.controller.U$$0.row_opened_LUT4_D_1_Z_L6MUX21_Z_D1_PFUMX_Z_SLICE.OFX0
Info:  0.0  4.5    Net dramcore.controller.U$$0.row_opened_LUT4_D_1_Z_L6MUX21_Z_D1 budget 0.000000 ns (13,79) -> (13,79)
Info:                Sink dramcore.controller.U$$0.row_opened_LUT4_D_1_Z_L6MUX21_Z_D1_PFUMX_Z_SLICE.FXB
Info:  0.2  4.7  Source dramcore.controller.U$$0.row_opened_LUT4_D_1_Z_L6MUX21_Z_D1_PFUMX_Z_SLICE.OFX1
Info:  0.5  5.3    Net dramcore.controller.U$$0.row_opened_LUT4_D_1_Z[2] budget 0.196000 ns (13,79) -> (13,78)
Info:                Sink dramcore.controller.U$$0.U$$1.source__payload__we_LUT4_B_Z_PFUMX_ALUT_SLICE.D1
Info:  0.3  5.6  Source dramcore.controller.U$$0.U$$1.source__payload__we_LUT4_B_Z_PFUMX_ALUT_SLICE.OFX0
Info:  0.0  5.6    Net dramcore.controller.U$$0.U$$1.source__payload__we_LUT4_B_Z_PFUMX_ALUT_Z budget 0.000000 ns (13,78) -> (13,78)
Info:                Sink dramcore.controller.multiplexer.tccdcon.ready_LUT4_D_Z_LUT4_Z_3_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_SLICE.FXA
Info:  0.2  5.7  Source dramcore.controller.multiplexer.tccdcon.ready_LUT4_D_Z_LUT4_Z_3_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_SLICE.OFX1
Info:  0.0  5.7    Net dramcore.controller.multiplexer.tccdcon.ready_LUT4_D_Z_LUT4_Z_3_D_L6MUX21_Z_D1 budget 0.000000 ns (13,78) -> (13,78)
Info:                Sink dramcore.controller.U$$0.U$$1.source__payload__we_LUT4_B_Z_PFUMX_ALUT_SLICE.FXB
Info:  0.2  5.9  Source dramcore.controller.U$$0.U$$1.source__payload__we_LUT4_B_Z_PFUMX_ALUT_SLICE.OFX1
Info:  0.7  6.7    Net dramcore.controller.multiplexer.tccdcon.ready_LUT4_D_Z_LUT4_Z_3_D[3] budget 0.392000 ns (13,78) -> (16,77)
Info:                Sink dramcore.controller.multiplexer.tccdcon.ready_LUT4_D_Z_LUT4_Z_2_SLICE.D1
Info:  0.2  6.8  Source dramcore.controller.multiplexer.tccdcon.ready_LUT4_D_Z_LUT4_Z_2_SLICE.F1
Info:  0.9  7.7    Net dramcore.controller.multiplexer.tccdcon.ready_LUT4_D_Z[1] budget 0.609000 ns (16,77) -> (16,80)
Info:                Sink dramcore.controller.U$$4.row_opened_TRELLIS_FF_Q_DI_LUT4_C_Z_L6MUX21_Z_D1_PFUMX_Z_SLICE.B1
Info:  0.3  8.0  Source dramcore.controller.U$$4.row_opened_TRELLIS_FF_Q_DI_LUT4_C_Z_L6MUX21_Z_D1_PFUMX_Z_SLICE.OFX0
Info:  0.0  8.0    Net dramcore.controller.U$$4.row_opened_TRELLIS_FF_Q_DI_LUT4_C_Z_L6MUX21_Z_D1 budget 0.000000 ns (16,80) -> (16,80)
Info:                Sink dramcore.controller.U$$4.row_opened_TRELLIS_FF_Q_DI_LUT4_C_Z_L6MUX21_Z_D1_PFUMX_Z_SLICE.FXB
Info:  0.2  8.2  Source dramcore.controller.U$$4.row_opened_TRELLIS_FF_Q_DI_LUT4_C_Z_L6MUX21_Z_D1_PFUMX_Z_SLICE.OFX1
Info:  1.3  9.5    Net dramcore.controller.U$$4.row_opened_LUT4_D_Z[3] budget 1.316000 ns (16,80) -> (16,89)
Info:                Sink dramcore.controller.U$$4.trccon.ready_LUT4_D_Z_LUT4_Z_SLICE.C1
Info:  0.2  9.7  Source dramcore.controller.U$$4.trccon.ready_LUT4_D_Z_LUT4_Z_SLICE.F1
Info:  0.9 10.6    Net dramcore.controller.U$$4.trccon.ready_TRELLIS_FF_Q_DI[3] budget 1.316000 ns (16,89) -> (16,90)
Info:                Sink dramcore.controller.U$$4.trascon.count_TRELLIS_FF_Q_2_DI_LUT4_Z_SLICE.D1
Info:  0.2 10.7  Source dramcore.controller.U$$4.trascon.count_TRELLIS_FF_Q_2_DI_LUT4_Z_SLICE.F1
Info:  0.6 11.3    Net dramcore.controller.U$$4.trascon.ready_TRELLIS_FF_Q_CE budget 1.316000 ns (16,90) -> (16,89)
Info:                Sink dramcore.controller.U$$4.trccon.ready_LUT4_D_Z_LUT4_Z_SLICE.CE
Info:  0.0 11.3  Setup dramcore.controller.U$$4.trccon.ready_LUT4_D_Z_LUT4_Z_SLICE.CE
Info: 3.4 ns logic, 7.9 ns routing
ERROR: Max frequency for clock         '$glbnet$sysclk_clk': 88.53 MHz (FAIL at 100.00 MHz)
Info: Max frequency for clock    '$glbnet$sysclk_init_clk': 306.47 MHz (PASS at 25.00 MHz)
ERROR: Max frequency for clock '$glbnet$sysclk_clk100_0__i': 99.42 MHz (FAIL at 100.00 MHz)

Info: Max delay <async>                            -> <async>                        : 0.98 ns
Info: Max delay posedge $glbnet$sysclk_clk         -> <async>                        : 5.48 ns
Info: Max delay posedge $glbnet$sysclk_clk100_0__i -> <async>                        : 9.60 ns
Info: Max delay posedge $glbnet$sysclk_clk100_0__i -> posedge $glbnet$sysclk_clk     : 9.75 ns
Info: Max delay posedge $glbnet$sysclk_clk100_0__i -> posedge $glbnet$sysclk_init_clk: 9.35 ns
Info: Max delay posedge $glbnet$sysclk_init_clk    -> <async>                        : 2.56 ns
Info: Max delay posedge $glbnet$sysclk_init_clk    -> posedge $glbnet$sysclk_clk     : 2.94 ns

Info: Slack histogram:
Info:  legend: * represents 18 endpoint(s)
Info:          + represents [1,18) endpoint(s)
Info: [ -1295,   2929) |************************************************************ 
Info: [  2929,   7153) |*************************+
Info: [  7153,  11377) |*********************+
Info: [ 11377,  15601) | 
Info: [ 15601,  19825) | 
Info: [ 19825,  24049) | 
Info: [ 24049,  28273) | 
Info: [ 28273,  32497) |+
Info: [ 32497,  36721) | 
Info: [ 36721,  40945) |*+
Info: [ 40945,  45169) | 
Info: [ 45169,  49393) | 
Info: [ 49393,  53617) | 
Info: [ 53617,  57841) | 
Info: [ 57841,  62065) | 
Info: [ 62065,  66289) | 
Info: [ 66289,  70513) | 
Info: [ 70513,  74737) |+
Info: [ 74737,  78961) |+
Info: [ 78961,  83185) |*+
jeanthom commented 4 years ago

Setting https://github.com/jeanthom/gram/blob/master/gram/core/refresher.py#L121-L124 as a sync statement breaks down the critical path (but also breaks the elaboratable behavior).

jeanthom commented 4 years ago

Issue partially mitigated with https://github.com/jeanthom/gram/commit/33d692fa6dd71b58fdcd98779a60323c0ea04ff9

jeanthom commented 4 years ago

Current critical path:

Info: Critical path report for clock '$glbnet$sysclk_clk' (posedge -> posedge):
Info: curr total
Info:  0.3  0.3  Source dramcore.controller.U$$3.row_TRELLIS_FF_Q_11_SLICE.Q0
Info:  0.8  1.1    Net dramcore.controller.U$$3.row[3] budget 0.403000 ns (33,40) -> (33,40)
Info:                Sink dramcore.controller.U$$3.trascon.ready_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_Z_SD_L6MUX21_Z_D1_PFUMX_Z_SLICE.B1
Info:  0.2  1.3  Source dramcore.controller.U$$3.trascon.ready_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_Z_SD_L6MUX21_Z_D1_PFUMX_Z_SLICE.OFX0
Info:  0.0  1.3    Net dramcore.controller.U$$3.trascon.ready_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_Z_SD_L6MUX21_Z_D1 budget 0.000000 ns (33,40) -> (33,40)
Info:                Sink dramcore.controller.U$$3.trascon.ready_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_Z_SD_L6MUX21_Z_D1_PFUMX_Z_SLICE.FXB
Info:  0.1  1.5  Source dramcore.controller.U$$3.trascon.ready_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_Z_SD_L6MUX21_Z_D1_PFUMX_Z_SLICE.OFX1
Info:  0.7  2.1    Net dramcore.controller.U$$3.trascon.ready_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_Z_SD[3] budget 0.402000 ns (33,40) -> (32,37)
Info:                Sink dramcore.controller.U$$3.trascon.ready_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_SLICE.D1
Info:  0.2  2.4  Source dramcore.controller.U$$3.trascon.ready_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_SLICE.OFX0
Info:  0.0  2.4    Net dramcore.controller.U$$3.trascon.ready_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_Z_D1_L6MUX21_Z_D1 budget 0.000000 ns (32,37) -> (32,37)
Info:                Sink dramcore.controller.U$$3.trascon.ready_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_SLICE.FXB
Info:  0.1  2.5  Source dramcore.controller.U$$3.trascon.ready_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_SLICE.OFX1
Info:  0.0  2.5    Net dramcore.controller.U$$3.trascon.ready_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_Z_D1 budget 0.000000 ns (32,37) -> (32,37)
Info:                Sink dramcore.controller.U$$3.trascon.ready_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_SLICE.FXB
Info:  0.1  2.7  Source dramcore.controller.U$$3.trascon.ready_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_SLICE.OFX1
Info:  1.5  4.1    Net dramcore.controller.U$$3.trascon.ready_LUT4_A_Z_PFUMX_ALUT_Z[2] budget 0.503000 ns (32,37) -> (27,56)
Info:                Sink dramcore.controller.U$$3.U$$1.source__payload__we_LUT4_B_1_Z_PFUMX_ALUT_SLICE.D1
Info:  0.2  4.3  Source dramcore.controller.U$$3.U$$1.source__payload__we_LUT4_B_1_Z_PFUMX_ALUT_SLICE.OFX0
Info:  0.0  4.3    Net dramcore.controller.U$$3.U$$1.source__payload__we_LUT4_B_1_Z_PFUMX_ALUT_Z budget 0.000000 ns (27,56) -> (27,56)
Info:                Sink dramcore.controller.U$$3.U$$1.source__payload__we_LUT4_B_1_Z_PFUMX_ALUT_Z_L6MUX21_D0_D1_PFUMX_Z_SLICE.FXA
Info:  0.1  4.5  Source dramcore.controller.U$$3.U$$1.source__payload__we_LUT4_B_1_Z_PFUMX_ALUT_Z_L6MUX21_D0_D1_PFUMX_Z_SLICE.OFX1
Info:  0.0  4.5    Net dramcore.controller.U$$3.U$$1.source__payload__we_LUT4_B_1_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z budget 0.000000 ns (27,56) -> (27,56)
Info:                Sink dramcore.controller.U$$3.U$$1.source__payload__we_LUT4_B_1_Z_PFUMX_ALUT_SLICE.FXB
Info:  0.1  4.6  Source dramcore.controller.U$$3.U$$1.source__payload__we_LUT4_B_1_Z_PFUMX_ALUT_SLICE.OFX1
Info:  0.5  5.1    Net dramcore.controller.multiplexer.choose_req.U$$0.grant_TRELLIS_FF_Q_DI_PFUMX_Z_C0_LUT4_Z_1_C_LUT4_Z_D[2] budget 0.502000 ns (27,56) -> (26,55)
Info:                Sink dramcore.controller.multiplexer.tccdcon.ready_LUT4_D_Z_LUT4_Z_SLICE.D1
Info:  0.1  5.3  Source dramcore.controller.multiplexer.tccdcon.ready_LUT4_D_Z_LUT4_Z_SLICE.F1
Info:  0.9  6.1    Net dramcore.controller.multiplexer.tccdcon.ready_LUT4_D_Z[1] budget 0.509000 ns (26,55) -> (23,57)
Info:                Sink dramcore.controller.U$$6.trascon.ready_LUT4_A_Z_PFUMX_Z_SLICE.C1
Info:  0.2  6.3  Source dramcore.controller.U$$6.trascon.ready_LUT4_A_Z_PFUMX_Z_SLICE.OFX0
Info:  1.3  7.6    Net dramcore.controller.U$$6.trascon.ready_LUT4_A_Z[4] budget 1.072000 ns (23,57) -> (22,47)
Info:                Sink dramcore.controller.U$$6.U$$0.fifo.r_en_LUT4_Z_SLICE.D1
Info:  0.1  7.8  Source dramcore.controller.U$$6.U$$0.fifo.r_en_LUT4_Z_SLICE.F1
Info:  1.1  8.8    Net dramcore.controller.U$$6.U$$0_source__ready budget 1.072000 ns (22,47) -> (22,48)
Info:                Sink dramcore.controller.U$$6.U$$0.fifo.storage.0.0.0$DPRAM1_SLICE.CE
Info:  0.0  8.8  Setup dramcore.controller.U$$6.U$$0.fifo.storage.0.0.0$DPRAM1_SLICE.CE
Info: 2.3 ns logic, 6.6 ns routing
jeanthom commented 4 years ago

~With NMIGEN_synth_opts set to "-retime -abc2" we can easily cut the resource usage in half and have a very comfortable max frequency for the design. Closing this issue.~

Yosys support for retiming is quite limite (no CDC annotations, etc.) so we better not use this.

jeanthom commented 4 years ago

Critical path seems improved thanks to dramsync rst fixes.