jeanthom / gram

DDR3 controller for nMigen (WIP)
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ECP5 CRG is wonky #23

Closed jeanthom closed 4 years ago

jeanthom commented 4 years ago

The current way of doing things is to use the PLL outside of its specs (ie. VCO=200Mhz, CLKOP divider=1, CLKFB=2). This should be avoided.