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jeanthom / gram

DDR3 controller for nMigen (WIP)
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Wishbone DRAM content interface debugging #6

Closed jeanthom closed 4 years ago

jeanthom commented 4 years ago

We can't currently run a memtest because the bus stalls when we do R/W accesses.

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jeanthom commented 4 years ago

gramWishbone FSM stalls in both Wait-Write and Wait-Read depending on if we're doing a write or read transaction

jeanthom commented 4 years ago

5 seems to have fixed the stall issue.