Bring back testing in gram

[jeanthom]

During the LiteDRAM -> dram I ditched all the simulation/test files. This is quite problematic, and should be addressed ASAP.

Ideas:

• Formal verification whenever possible
• Use SV models (Micron offers one)
  • HowTo SV with FOSS tools? HowTo DDR I/O modeling for the ECP5?

[jeanthom]

https://github.com/awersatos/AD/tree/master/Library/HDL%20Simulation/Lattice%20ispLEVER%208.0%20Verilog%20Libraries/ovi_ecp3/src has DDR models for ECP3. Can we reuse those models, or produce similar models for the ECP5?

[jeanthom]

Lattice Diamond provides simulation libraries for the ECP5 (in /usr/local/diamond/3.11_x64/ispfpga/verilog/data/ecp5u):

ALU24A.v
ALU24B.v
ALU54A.v
ALU54B.v
AND2.v
AND3.v
AND4.v
AND5.v
BBPD.v
BBPU.v
BB.v
BCINRD.v
BCLVDSOB.v
BUFBA.v
CCU2C.v
CLKDIVF.v
DCCA.v
DCSC.v
DDRDLLA.v
DELAYF.v
DELAYG.v
DLLDELD.v
DP16KD.v
DPR16X4C.v
DQSBUFM.v
DTR.v
ECLKBRIDGECS.v
ECLKSYNCB.v
EHXPLLL.v
EXTREFB.v
FD1P3AX.v
FD1P3AY.v
FD1P3BX.v
FD1P3DX.v
FD1P3IX.v
FD1P3JX.v
FD1S3AX.v
FD1S3AY.v
FD1S3BX.v
FD1S3DX.v
FD1S3IX.v
FD1S3JX.v
FL1P3AY_FUNC.v
FL1P3AY.v
FL1P3AZ_FUNC.v
FL1P3AZ.v
FL1P3BX_FUNC.v
FL1P3BX.v
FL1P3DX_FUNC.v
FL1P3DX.v
FL1P3IY_FUNC.v
FL1P3IY.v
FL1P3JY_FUNC.v
FL1P3JY.v
FL1S3AX.v
FL1S3AY.v
GSR.v
IBPD.v
IBPU.v
IB.v
IDDR71B.v
IDDRX1F.v
IDDRX2DQA.v
IDDRX2F.v
IFS1P3BX.v
IFS1P3DX.v
IFS1P3IX.v
IFS1P3JX.v
IFS1S1B.v
IFS1S1D.v
IFS1S1I.v
IFS1S1J.v
ILVDS.v
IMIPI.v
INRDB.v
INV.v
L6MUX21.v
LUT4.v
LUT5.v
LUT6.v
LUT7.v
LUT8.v
lut_mux2.v
lut_mux4.v
LVDSOB.v
MULT18X18C.v
MULT18X18D.v
MULT9X9C.v
MULT9X9D.v
MUX161.v
MUX21.v
MUX321.v
MUX41.v
MUX81.v
ND2.v
ND3.v
ND4.v
ND5.v
NR2.v
NR3.v
NR4.v
NR5.v
OBCO.v
OB.v
OBZPD.v
OBZPU.v
OBZ.v
ODDR71B.v
ODDRX1F.v
ODDRX2DQA.v
ODDRX2DQSB.v
ODDRX2F.v
OFS1P3BX.v
OFS1P3DX.v
OFS1P3IX.v
OFS1P3JX.v
OLVDS.v
OR2.v
OR3.v
OR4.v
OR5.v
OSCG.v
OSHX2A.v
PCSCLKDIV.v
PDPW16KD.v
PFMUX.v
PFUMX.v
PLLREFCS.v
PRADD18A.v
PRADD9A.v
PUR.v
ROM128X1A.v
ROM16X1A.v
ROM256X1A.v
ROM32X1A.v
ROM64X1A.v
SCCU2C.v
SDPRAME.v
SEDGA.v
SGSR.v
SLOGICB.v
SPR16X4C.v
SRAMWB.v
START.v
TSHX2DQA.v
TSHX2DQSA.v
UDFDL1_UDP_X.v
UDFDL3_UDP_X.v
UDFDL4E_UDP_X.v
UDFDL4SC_UDP_X.v
UDFDL5E_UDP_X.v
UDFDL5SC_UDP_X.v
UDFDL5_UDP_X.v
UDFDL6E_UDP_X.v
UDFDL6SP_UDP_X.v
UDFDL7E_UDP_X.v
UDFDL7SP_UDP_X.v
UDFDL7_UDP_X.v
USRMCLK.v
VHI.v
VLO.v
XNOR2.v
XNOR3.v
XNOR4.v
XNOR5.v
XOR11.v
XOR21.v
XOR2.v
XOR3.v
XOR4.v
XOR5.v

[jeanthom]

PoC code with Lattice ECP5 instances published in https://github.com/jeanthom/gram/commit/0c6d000f65ed15929ffb475667605c43b3baab54

[jeanthom]

Currently our simulation code is quite slow because we're using unsynthesizable code in Icarus Verilog. We could use a synthesizable model to make things faster. There's this one which is opensource: https://github.com/freecores/ddr3_synthesizable_bfm

But it isn't flexible enough to emulate a RAM chip with two (or more) DQS signals.

[jeanthom]

Untested classes:

• gram.core
  • [ ] gramCore
  • gram.core.bankmachine
    • [x] _AddressSlicer
    • [ ] BankMachine
  • gram.core.controller
    • [ ] ControllerSettings
    • [ ] gramController
  • gram.core.crossbar
    • [ ] gramCrossbar
  • gram.core.multiplexer
    • [x] _CommandChooser
    • [x] _Steerer
    • [ ] Multiplexer
  • gram.core.refresher
    • [x] ZQCSExecuter
    • [ ] Refresher
• gram.phy
  • [ ] ECP5DDRPHYInit