Memtest fail

[jeanthom]

Memtest is currently failing, investigation in progress.

[jeanthom]

Every readout in the DDR region returns 0x00000003.

[jeanthom]

• [ ] The way we do CRG could be an issue (in LiteDRAM the sys clock is generated from sys2x)
• [x] Bad init sequence
• [x] Communication issue with the native port

[jeanthom]

We're getting something interesting:

# Route data reads -------------------------------------------------------------------------
for master in self.masters:
    #m.d.comb += master.rdata.data.eq(controller.rdata)
    m.d.comb += master.rdata.data.eq(0xAF)

(gram/core/crossbar.py:216)

We're reading *(0x10000000) = FAFAFAF3 instead of AFAFAFAF.

That very specific issue seems located between gramWishbone and gramCrossbar.

[jeanthom]

Readout issue fixed in #8. Now the issue seems located in the PHY

[jeanthom]

Current issue is wishbone front end stuck in "Wait-Read" state.

[jeanthom]

~Multiplexer doesn't seem stuck in a particular state.~ It actually juggles between read and refresh states.

[jeanthom]

Here's what we currently get from a simple memory test (writing 0x12345678):

0x10000000 = 91a2b3c0
0x10000004 = 12005600
0x10000008 = 12ff56ff
0x1000000c = 12345678
0x10000010 = 12005600
0x10000014 = 12ff56ff
0x10000018 = 12345678
0x1000001c = 12005600
0x10000020 = 12345678
0x10000024 = 12005600
0x10000028 = 12ff56ff
0x1000002c = 12345678
0x10000030 = 12005600
0x10000034 = 12ff56ff
0x10000038 = 12345678
0x1000003c = 12005600
0x10000040 = 12345678
0x10000044 = 12005600

We're getting there!

EDIT/ The above result is actually expected: we are directly reading off the native port which hasn't the same bus size as our wishbone bus.

[jeanthom]

29

[jeanthom]

We're seeing some improvement. Oddly enough, the "green data" pattern varies when I change the FPGA board...

[jeanthom]

35

[jeanthom]

Getting some good progress.

[jeanthom]