search

jeelabs / esp-link

esp8266 wifi-serial bridge, outbound TCP, and arduino/AVR/LPC/NXP programmer
Other
2.82k stars 720 forks source link

Why is the reset pin driven high instead of left floating when unasserted? #474

Closed GMMan closed 4 years ago

GMMan commented 4 years ago

I recently flashed esp-link to a D1 Mini clone and wired it into a consumer product that has an AllWinner R16 SoC and AXP233 PMIC. Everything worked fine out of the box except I had to issue a uC reset to get the SoC to actually enter FEL mode after setting it up to do so. I found that esp-link driving the RESET/PWROK line high was interfering with the SoC's watchdog reset. I changed all instances where esp-link drives the reset pin high to disabling output so it floats, and now the SoC is entering FEL mode as expected.

My question is why has esp-link been designed to drive reset high while idle? If a uC requires a specific powerup sequence, this would interfere with that. If the uC doesn't require a powerup sequence, the reset pin would have been pulled high on the board the uC is attached to anyway.

tve commented 4 years ago

Makes sense, didn't think of it and it never came up as a problem...

uzi18 commented 4 years ago

@GMMan @tve can look at it, should be possible to fix

Do you want to test bins? what flash files you usually use for module?

GMMan commented 4 years ago

This is what I'm using currently: https://github.com/GMMan/esp-link/tree/v3.0.14-floating-reset

My module is 4MB:512/512.

uzi18 commented 4 years ago

that's exactly what I wanted to do :) (change reset pin to input when not used) so if it works for you please create PR

GMMan commented 4 years ago

Should I rebase it on the master branch?