Report VHDL Reserved Words

[SittingDuc]

The VHDL LRM has a short list (I count 120) of reserved keywords that identifiers (signals, functions, labels, etc) cannot have - "signal", "port", "bus", "default", etc. Each new revision generally adds a few new words - "protected", "private", "context" etc. (I also count 4 words removed in the history of the standard)

At present nothing in vsg nor vscode alerts me that a given identifier has been given a reserved name, which is complicating my use-case - "make this VHDL-1993-ish code compile cleanly under VHDL-2008". For now I have a workaround of trying to compile the code in ModelSim, which is pretty good about protesting about the new keywords that it knows about, but a linter message would be nice too.

A useful feature would be a rule that checks each identifier is not on the set of reserved words. For myself, any word reserved from 1987 to 2019 is sufficient; but other users might appreciate "only test words from VHDL-2002" if that is the standard their project is being compiled to.

It is also worth noting that functions can sometimes be called operations - such as "nand", "xor", when overloading the defined operations; but that naming a signal "xor" is more likely an error.

Thanks,

[SittingDuc]

An example will help. The attached file passes vsg with no reported issues, despite almost every identifier in it being a reserved keyword

keyword_test.vhd.txt

With the proposed feature request, the test file will report a count of issues (8-14 depending on what is fair to trip a message)

Thanks again,

[jeremiah-c-leary]

Morning @SittingDuc ,

I pushed an update to the issue-1053 branch where I added the rule reserved_001. It has an option named standard and takes one of the following values: all, 1987, 1993, 2000, 2002, 2008. The default is all.

When you get a chance could you give a try and let me know what you think?

I need to improve my tests, but the example file you gave passes against the new rule.

Thanks,

--Jeremy

[SittingDuc]

Hello,

I grabbed a copy of the git tree on the branch issue-1053 and ran it over some files, real and artificial and it works, so the new test is good by me.

Reading over the code, I did note some symbols got duplicated in dMap['2008'] (file rule_001.py at or about line 26), 'assert', 'assume', 'assume_guarantee', 'cover', 'default', 'fairness', 'property', 'restrict', 'restrict_guarantee', 'sequence', 'strong', 'vmode', 'vprop', 'vunit'... looks like a copy-pasta

I have no objections to a merge. Thank you for your work on supporting my feature request! :)

[jeremiah-c-leary]

Morning @SittingDuc ,

Good catch on the duplicate entries. I have removed them.

I will merge this into master.

--Jeremy