search

jeremiah-c-leary / vhdl-style-guide

Style guide enforcement for VHDL
GNU General Public License v3.0
179 stars 38 forks source link

possible typo in process_021 python #1066

Closed SittingDuc closed 7 months ago

SittingDuc commented 7 months ago

Hello again,

Reviewing the configuration file changes from 3.18.0 to 3.19.0, I find process_021 has a default of "no_blank_line_line", line 64 of vsg/rules/process/rule_021.py

     60     def __init__(self):
     61         blank_line.Rule.__init__(self, 'process', '021')
     62         self.solution = 'Remove blank lines above *begin* keyword'
     63         self.phase = 1
     64         self.style = 'no_blank_line_line'
     65         self.configuration.append('style')

Given that "line_line" does not appear in any other file in the project, I expect this is a typo?

VHDL Style Guide (VSG) version: 3.19.0
Git commit SHA: c3e408e9

copied this morning

Cheers!

jeremiah-c-leary commented 7 months ago

Morning @SittingDuc ,

Good catch. I pushed an update to the issue-1066 branch. When you get a chance could you validate it on your end?

Thanks,

--Jeremy

SittingDuc commented 7 months ago

Hello. I have eyeballed the commit (but not run it up) and I see no typos in the fix for the typo :) Thanks

jeremiah-c-leary commented 7 months ago

Morning @SittingDuc ,

I will merge this to master.

--Jeremy