jeremiah-c-leary / vhdl-style-guide

Style guide enforcement for VHDL
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Add an "ignore_single_line" option to prcoedure_call_003 #1076

Closed JHertz5 closed 6 months ago

JHertz5 commented 7 months ago

Is your feature request related to a problem? Please describe. Some rules, such as Array Multiline Structure Rules, have an ignore_single_line option. I would like to have a similar option for the prcoedure_call_003 rule, so that I can enforce structure on multi-line procedure calls while leaving neat one-liners alone.

Describe the solution you'd like Input:

entity test is
end entity test;

architecture rtl of test is

begin

  lil_proc(actual_1);

  big_proc(
           formal_1 => actual_1,
           formal_2 => actual_2
         );

end architecture rtl;

Config

rule:
  procedure_call_003:
    first_open_paren: 'remove_new_line'
    last_close_paren: 'add_new_line'
    association_element: 'add_new_line'
    association_list_comma: 'ignore'
    ignore_single_line: 'yes'

Current output (ignoring the fact that ignore_single_line would break the current config):

entity test is
end entity test;

architecture rtl of test is

begin

  -- One-liner is no longer a one-liner.
  lil_proc(actual_1
         );

  big_proc(
           formal_1 => actual_1,
           formal_2 => actual_2
         );

end architecture rtl;

Desired output:

entity test is
end entity test;

architecture rtl of test is

begin

  -- One-liner is ignored.
  lil_proc(actual_1);

  big_proc(
           formal_1 => actual_1,
           formal_2 => actual_2
         );

end architecture rtl;
JHertz5 commented 7 months ago

I have had a go at actioning this issue and raised PR #1077. Any feedback is welcome.

jeremiah-c-leary commented 6 months ago

Good afternoon @JHertz5 ,

I reviewed the PR and it looks good.

Thank you for updating the documentation and the tests.

I will merge this to master.

--Jeremy