jeremiah-c-leary / vhdl-style-guide

Style guide enforcement for VHDL
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Have `procedure_call_400` align multi-line parameters with the assignment keyword #1078

Open JHertz5 opened 9 months ago

JHertz5 commented 9 months ago

Is your feature request related to a problem? Please describe.

Currently, procedure_call_400 produces the following code:

entity test is
end entity test;

architecture rtl of test is

begin

  my_proc(
    formal_1 => actual_1 +
    actual_2,
    formal_2 => "test_text" &
    "test_text"
  );

end architecture rtl;

Note that the second line of the parameter is aligned with the formal parameters rather than the actuals.

Describe the solution you'd like I would like to have it produce the following code:

entity test is
end entity test;

architecture rtl of test is

begin

  my_proc(
    formal_1 => actual_1 +
                actual_2,
    formal_2 => "test_text" &
                "test_text"
  );

end architecture rtl;

Would this be possible? No problem if not, this is definitely a "nice to have" feature.