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jeremiah-c-leary / vhdl-style-guide

Style guide enforcement for VHDL
GNU General Public License v3.0
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Add rules to enforce prefixes and suffixes on for generate/loop parameters #1110

Closed JHertz5 closed 5 months ago

JHertz5 commented 5 months ago

Describe the solution you'd like I would like to be able to enforce a prefix and/or suffix on parameters for generates and loops, e.g.

for index in t_range loop

becomes

for lv_index in t_range loop
JHertz5 commented 5 months ago

I am working on a PR for this, it should be raised today.

JHertz5 commented 5 months ago

I have raised PR #1111 for this issue. Any feedback is very welcome.

jeremiah-c-leary commented 5 months ago

Afternoon @JHertz5 ,

I reviewed the PR and it looks good. I was initially thinking there could be a single rule for the generate and loop statements since they both share the parameter_specification production. However, then you would not be able to set generate and loops to different prefixes and suffixes.

Overall the PR looks great. 1) documentation was created/updated 2) Tests were added 3) Rules added 4) Numbering of the rules are consistent with the current numbering method.

You even fixed some of my copy/paste documentation errors.

Excellent job!!!

I will get this merged to master.

Regards,

--Jeremy