Hang on malformed array range followed by unclosed port

[maltaisn]

Describe the bug The program hangs when parsing a port declaration with an unclosed parenthesis in an array range.

To Reproduce

bug.vhd

library ieee;
use ieee.std_logic_1164.all;

entity bug is
   port (
      data : in std_logic_vector(11 downto;  -- !!!
   -- !!!
end entity;

Execute the following command:

vsg -f bug.vhd --jobs 1

I used --jobs 1 otherwise the program cannot be stopped with a keyboard interrupt (is this expected?).

Expected behavior I'm not sure what's the expected behavior on malformed VHDL. I've seen crashes in some cases, but a hang is a bit more annoying.

[jeremiah-c-leary]

Good Evening @maltaisn ,

I just pushed an update for this to the issue-1123 branch. I added an exception to catch this case an report an error message. When you get a chance can you try it on your end and let me know what you think?

Thanks,

--Jeremy

[maltaisn]

It still hangs. I'm doing:

bin/vsg -f bug.vhd --jobs 1

Is this ok?

I tried with python setup.py install too but I get the same result.

[jeremiah-c-leary]

Evening @maltaisn ,

You will need to pull down the issue-1123 branch and then re-run the command.

Using your code snippet I get the following outp;ut:

$ vsg -f original.vhd --jobs 1

Error: Closing token not found while parsing Line 6

 6 |       data : in std_logic_vector(11 downto;  -- !!!

Let me know if you need any help with getting to the branch.

Regards,

--Jeremy

[maltaisn]

It works. I had just mixed the two issues. Thank you for the quick fixes.

[jeremiah-c-leary]

Awesome,

I will get this merged to master.

--Jeremy