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jeremiah-c-leary / vhdl-style-guide

Style guide enforcement for VHDL
GNU General Public License v3.0
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port_026 missing closing parenthesis in split ports #1124

Closed maltaisn closed 4 months ago

maltaisn commented 5 months ago

Describe the bug The port_026 rule misses a closing parenthesis in some circumstances.

To Reproduce

bug.vhd
library ieee;
use ieee.std_logic_1164.all;

entity bug is
   port (
      ain1, ain2 : in std_logic_vector(11 downto 0);
      out1, out2 : out std_logic_vector(12 downto 0));
end entity bug;

The following command is executed:

vsg -f bug.vhd --fix

The resulting file:

bug.vhd
library ieee;
  use ieee.std_logic_1164.all;

entity bug is
  port (
    ain1 : in    std_logic_vector(11 downto 0);
    ain2 : in    std_logic_vector(11 downto 0);
    out1 : out   std_logic_vector(12 downto 0;    -- !!!
    out2 : out   std_logic_vector(12 downto 0)
  );
end entity bug;

I'm using vsg v3.20.0

Expected behavior A parenthesis is missing.

jeremiah-c-leary commented 5 months ago

Good Afternoon @maltaisn ,

Thank you for finding this issue. I pushed an update to the issue-1124 branch. When you get a chance could you check it out on your end and let me know it works for you?

Thanks,

--Jeremy

maltaisn commented 4 months ago

It works.

jeremiah-c-leary commented 4 months ago

Awesome, merging to master.

--Jeremy