jeremiah-c-leary / vhdl-style-guide

Style guide enforcement for VHDL
GNU General Public License v3.0
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Rule for "space around operators" (?) #1171

Open ungultig1 opened 1 month ago

ungultig1 commented 1 month ago

Hi there,

i couldn't find the following rule yet, so could be included in future releases.

I'd like to have a format rule for this case, where it inserts a single space before and after operators:

violation:

if (readAddr>=writeAddr) then
 ...
end if;

Fix:

if (readAddr >= writeAddr) then
 ...
end if;

Thank you.

Greetings,

jeremiah-c-leary commented 1 month ago

Evening @ungultig1 ,

You are correct, there is no rule for whitespace around most operators. I am currently away from a computer until June 2nd. I will add a rule shortly after that date.

Regards,

--Jeremy

jeremiah-c-leary commented 1 month ago

Morning @ungultig1 ,

I have pushed an update for this issue to the issue-1171 branch. When you get a chance could you validate it on your end and let me know if it is working on your end?

Thanks,

--Jeremy

jeremiah-c-leary commented 2 weeks ago

Morning @ungultig1 ,

Just wanted to ping you to see if you had a chance to check out the update.

Thanks,

--Jeremy

domWalters commented 2 days ago

@jeremiah-c-leary I'm currently getting your tool working in my workflow and was looking for exactly this rule.

Hopefully I'll be able to test this at some point tomorrow.

Leaving this comment to hopefully remind me 😊

jeremiah-c-leary commented 15 hours ago

Morning @domWalters ,

It would be great if you could validate this issue.

--Jeremy