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jeremiah-c-leary / vhdl-style-guide

Style guide enforcement for VHDL
GNU General Public License v3.0
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Parsing fails for external names pathnames that include a parenthesis not at the end of the pathname #1243

Closed JHertz5 closed 1 month ago

JHertz5 commented 1 month ago

Environment VSG's current master (at time of writing) git hash:

ce86655850d0e24df420e3799b9b5036596a820d

Describe the bug An external pathnames can have parenthesis in them, for example if there is a for generate statement in the path. At the moment, when the external names rules are run on a path that includes a parenthesis with anything after the parenthesis, VSG fails with an error.

To Reproduce Steps to reproduce the behavior:

  1. Create a file "test.vhd" with the following contents: 
    
architecture rtl of test is

begin

-- Problem here. count_output <= << signal .gen(gv_counter).o_count : t_count >>;

-- This works fine. count_output <= << signal .gen(gv_counter) : t_count >>;

end architecture rtl;

2. Run `vsg -f test.vhd`
3. Observe the output

Error while processing test.vhd: Error: Unexpected token detected while parsing external_signal_name @ Line 6, Column 41 in file None Expecting : : Found : .o_count



**Expected behavior**
I expect the tool to be able to function normally on this kind of statement.
JHertz5 commented 1 month ago

I have found the source of the problem and I plan to raise a pull request to address it soon.

JHertz5 commented 1 month ago

I've created PR #1244 to resolve this issue.

jeremiah-c-leary commented 1 month ago

Morning @JHertz5 ,

Thanks for the pull request.

I have not used external names before so it is challenging to create testcases. It would be nice if there was some standard set of files that could be used to run parsers against.

I will get this merged to master.

--Jeremy