JHertz5
commented
5 days ago Hi @ArnePret. I believe that the problem here is the configuration in your Style.yaml file, not a bug in VSG. Your configuration sets the regex to "= '[A-Za-z]*'", i.e. the regex will not be satisfied unless there is an equals sign and a space at the start of your architecture name (which is obviously not valid VHDL). If you remove the =, I think that your problem will be solved.
Test
Corrected yaml file, test.yml:
rule:
architecture_013:
case: 'regex'
regex: '[A-Za-z]*'Upper Case
Test input file, test.vhd
architecture RTL of test is
begin
end architecture rtl;VSG output:
$ ./bin/vsg -f test.vhd -c test.yml
================================================================================
File: test.vhd
================================================================================
Phase 7 of 7... Reporting
Total Rules Checked: 769
Total Violations: 0
Error : 0
Warning : 0Lower Case
Test input file, test.vhd
architecture rtl of test is
begin
end architecture rtl;VSG output:
$ ./bin/vsg -f test.vhd -c test.yml
================================================================================
File: test.vhd
================================================================================
Phase 7 of 7... Reporting
Total Rules Checked: 769
Total Violations: 0
Error : 0
Warning : 0Mixed Case
Test input file, test.vhd
architecture RtL of test is
begin
end architecture rtl;VSG output:
$ ./bin/vsg -f test.vhd -c test.yml
================================================================================
File: test.vhd
================================================================================
Phase 7 of 7... Reporting
Total Rules Checked: 769
Total Violations: 0
Error : 0
Warning : 0I hope this helps, let me know if the problem persists on your end.
jeremiah-c-leary
Environment VSG 3.26.0 Windows 11 TerosHDL v6.0.10 (with VSG selected as VHDL formatter)
Describe the bug When trying to Configuring Uppercase and Lowercase Rules the regex option appears to be doing nothing. Currently a lot of prefix_exceptions are defined in my Style.yaml, which all work fine. It would be a lot less work though, to write one line of regex and be done with it. But regex never matches anything for me.
To Reproduce Install VSCode Install TerosHDL (follow instructions on their website) Configure VSG as selected VHDL formatter Link yaml stylesheet
In Style.yaml: architecture_013: case: 'regex' regex: = '[A-Za-z]*'
In vhdl file: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.math_real.all;
entity Test is end entity Test;
architecture arch of Test is
begin
end architecture arch;
Expected behavior Accept arch as correct, since it matches the regex.
Screenshots