Environment v3.27.0

Describe the bug generic_map_006 enforces a single space between the map keyword and open parentheses in generic maps. However, I have discovered that this rule also triggers on prt maps, which should be outside the scope of the rule.

To Reproduce Steps to reproduce the behavior:

Create a file test.vhd
```
architecture rtl of test is
```

begin

cmp_test : component test port map( clk => clk, reset => reset );

end architecture rtl;

2. Run `vsg -f test.vhd`
3. Observe output

$ vsg -f test.vhd

File: test.vhd

Phase 7 of 7... Reporting Total Rules Checked: 807 Total Violations: 1 Error : 1 Warning : 0 ----------------------------+------------+------------+-------------------------------------- Rule | severity | line(s) | Solution ----------------------------+------------+------------+-------------------------------------- generic_map_006 | Error | 6 | Add 1 space(s) between map and ( ----------------------------+------------+------------+-------------------------------------- NOTE: Refer to online documentation at https://vhdl-style-guide.readthedocs.io/en/latest/index.html for more information.



**Expected behavior**
I would expect there to be a separate rule to enforce this formatting for port maps.

jeremiah-c-leary / vhdl-style-guide

`generic_map_006` produces error on port maps #1316

$ vsg -f test.vhd

File: test.vhd