jeremiah-c-leary / vhdl-style-guide

Style guide enforcement for VHDL
GNU General Public License v3.0
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Rules to enforce `map` keyword on the same line as the `generic` or `port` keywords. #1320

Open JHertz5 opened 1 week ago

JHertz5 commented 1 week ago

Is your feature request related to a problem? Please describe. I would like rules to enforce the map keyword being on the same line as the generic or port keywords, with no more than one space. For example the following code raises no errors.

architecture rtl of test is

begin

  cmp_test : component test_2
    generic
      map (
      g_test => c_test
    )
    port
      map (
      clk   => clk,
      reset => reset
    );

end architecture rtl;
architecture rtl of test is

begin

  cmp_test : component test_2
    generic     map (
      g_test => c_test
    )
    port    map (
      clk   => clk,
      reset => reset
    );

end architecture rtl;

I would like both of these code snippets to raise errors/fix to this

architecture rtl of test is

begin

  cmp_test : component test_2
    generic map (
      g_test => c_test
    )
    port map (
      clk   => clk,
      reset => reset
    );

end architecture rtl;
JHertz5 commented 1 week ago

I've raised PR #1321 to resolve this issue.