jeremiah-c-leary / vhdl-style-guide

Style guide enforcement for VHDL
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Add indent and blank line rules for package instantiation declarations #1323

Open JHertz5 opened 1 week ago

JHertz5 commented 1 week ago

Subtask of #1306. Implement indent and blank line rules for package instantiation declarations.

For example, rules to fix this

library ieee;
  use ieee.std_logic_1164.all;
      package my_pkg is new my_generic_pkg
  generic map (
    g_my_generic => 2
  );

to this

library ieee;
  use ieee.std_logic_1164.all;

package my_pkg is new my_generic_pkg
  generic map (
    g_my_generic => 2
  );
JHertz5 commented 1 week ago

I've raised a PR https://github.com/jeremiah-c-leary/vhdl-style-guide/pull/1327 to resolve this issue.