jeremiah-c-leary / vhdl-style-guide

Style guide enforcement for VHDL
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case generate when : alignment and capitalization rules #800

Closed oletf closed 2 years ago

oletf commented 2 years ago

Hi, could it be possible to get rules for case generate when alignment as well as capitalization (for the others keyword) ?

I got this :

fc : for I IN comb_in'range generate

    gc : case I generate
      when 1 =>
         -- entity
      when n_order =>
         -- entity
      when OTHERS         =>
         -- entity
    end generate gc;

  end generate fc;

and it'd be very nice if vsg turned it into this :

fc : for I IN comb_in'range generate

    gc : case I generate
      when 1       =>
         -- entity
      when n_order =>
         -- entity
      when others  =>
         -- entity
    end generate gc;

  end generate fc;

thanks forward

jeremiah-c-leary commented 2 years ago

Hey @oletf,

I can add the alignment and case rules.

--Jeremy

jeremiah-c-leary commented 2 years ago

Hey @oletf,

I pushed an update for this to the issue-800 branch. When you get a chance could you check it out and let me know how it works for you.

In order to get the => aligned you will have to enable rule case_generate_statement_400 using the following configuration:

rule:
  case_generate_statement_400:
    disable: False

Thanks,

--Jeremy

oletf commented 2 years ago

Hi,

Just checked it, works good for me. 👍

jeremiah-c-leary commented 2 years ago

Hey @oletf,

Awesome!!! I will merge this into master.

--Jeremy