jeremiah-c-leary / vhdl-style-guide

Style guide enforcement for VHDL
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No columns-movement for signals inside constant declrations #999

Closed ungultig1 closed 12 months ago

ungultig1 commented 1 year ago

Hello,

i checked settings for "constant"-adjustments, but could not find any solution regarding this issue:

It moves columns for the record, but not for the constant declaration:

type t_my_rec is record
    signal_one       : std_logic;
    signal_onetwo    : std_logic;
end record my_rec ;

constant my_rec : t_my_rec :=
(
    signal_one => '0',
    signal_onetwo => '0'
);

Expected:

type t_my_rec is record
    signal_one       : std_logic;
    signal_onetwo    : std_logic;
end record my_rec ;

constant my_rec : t_my_rec :=
(
    signal_one       => '0',
    signal_onetwo    => '0'
);

Any plans to include this also?

Thx.

jeremiah-c-leary commented 1 year ago

Good Morning @ungultig1 ,

I pushed an update for this issue to the issue-999 branch.

I added rule constant_400 which will align the => in constant declarations.

When you get a chance could you check it out and let me know how it goes?

Thanks,

--Jeremy

ungultig1 commented 12 months ago

Good Afternoon @jeremiah-c-leary ,

i tested the column-movement for constant declarations. It works perfect.

Thank you for fixing.

Greetings,

jeremiah-c-leary commented 12 months ago

Awesome, I will merge this to master.

--Jeremy