Decide if the whole project should be converted to UVM

jerralph / riscv-vip

For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug

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Decide if the whole project should be converted to UVM #1

Closed jerralph closed 5 years ago

jerralph commented 6 years ago

Converting the entire riscv-vip to use the UVM base classes has pros and cons. Initially I tried to have basic SystemVerilog classes that weren't based on UVM, then have a UVM wrapper for integration into UVM environments.

If any potential users have opinions I'd appreciate your input.

Pros for UVM:

handy reporting
field utilities (copy, compare, ...)
factory substitution capabilities

Cons for UVM:

users need to know (or learn) UVM

jerralph commented 5 years ago

Decided that we'll go all UVM and moving in this direction with the all-uvm-dev branch and the "UVM Merge to Master" milestone.